1. The Field of the Invention
The present invention relates to the fabrication of microelectronic semiconductor devices. More particularly, the present invention relates to the fabrication of metallization lines. In particular, the present invention relates to a metallization line layout optimization to avoid depth of field sensitivity and excess reflectance in isolated metallization lines. Additionally, the present invention achieves a substantially planar dielectric layer upper surface, upon deposition and without further processing, of the dielectric layer over the inventive metallization line layout.
2. The Relevant Technology
In the microelectronics industry, a substrate refers to one or more semiconductor layers or structures which includes active or operable portions of semiconductor devices. In the context of this document, the term xe2x80x9csemiconductive substratexe2x80x9d is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term xe2x80x9csubstratexe2x80x9d refers to any supporting structure including but not limited to the semiconductive substrates described above.
Following the formation of semiconductor devices, the devices need to be electrically connected, either to themselves or to the outside world to make the semiconductor device function as part of a greater whole. The electrical connection of the semiconductor devices is carried out by the metallization process. Metallization comprises the layout and patterning of a series of electrically conductive lines upon an upper surface of a substrate. The metallization lines make electrical connection, through either vias or interconnects, between individual semiconductor devices and/or the outside world.
FIG. 1 illustrates a plan view of a typical xe2x80x9cManhattanxe2x80x9d style metallization line layout 10, by way of non-limiting example, at least a portion of a metal-1 layout for a sense amplifier. A Manhattan style metallization layout may also be called a rectangular, or right-angle rectilinear metallization layout. Such a metallization layout is characterized by raised, elongate structures that have only substantially right-angle deviations from being straight or linear. The term xe2x80x9cverticalxe2x80x9d is intended to mean a direction between the top and bottom of the page of a figure. The term xe2x80x9clateralxe2x80x9d is intended to means a sideways direction of a figure, substantially orthogonal to xe2x80x9cvertical.xe2x80x9d
Referring to FIG. 1, arbitrary region Z is seen in FIG. 1 to have a substantially rectangular shape that includes parallel vertical boundaries 15, 15xe2x80x2 and parallel horizontal boundaries 17, 17xe2x80x2. Metallization lines include isolated lines and may be shown as having an end 11 within an arbitrary region Z. Metallization lines include continuous lines and are shown as extending substantially across FIG. 1 with no end found within arbitrary region Z. For example, isolated line 1-left (isolated line 1L) is defined as having end 11 within arbitrary region Z of metallization line layout 10, and arbitrary region Z does not include a physical edge of metallization line layout 10. An xe2x80x9cendxe2x80x9d 11 is defined as a portion of a metallization line that discontinues within arbitrary region Z and that has a length that may be substantially the width W of the metallization line for a length along the same metallization line at least equal to the distance W.
It is noted that in the prior art xe2x80x9cManhattanxe2x80x9d layout of metallization line layout 10, ends 11 for all of isolated lines 1R-11R are all a fixed distance 27 from a closest vertical boundary 15 of arbitrary region Z, or a fixed distance 29 from a closest boundary 15xe2x80x2.
A continuous line is defined as having no end within arbitrary region Z of metallization line layout 10. For example, continuous line 3 has no end within arbitrary region Z depicted as FIG. 1. Continuous line 3 has an enlarged feature 13.
FIG. 1 illustrates several occurrences of isolated lines and continuous lines. As used herein, an xe2x80x9cintersectionxe2x80x9d is defined as a subregion within arbitrary region Z at which at least one end of a metallization line occurs. The four top-most metallization lines in FIG. 1 are demarcated as isolated lines 1L and 2L and isolated lines 1R and 2R. The next metallization line down is a continuous metallization line and is thus demarcated as continuous line 3.
An intersection is defined as a portion of a layout with at least one end 11. The intersection may be bordered by a continuous line. For example, a 6-way intersection occurs at the demarcation X where it can be seen that a 6-arrowed illustrative figure has been drawn to demonstrate the 6-way nature of this intersection. Intersection X is bordered by continuous lines 6 and 9. Intersection X includes the spaces between continuous line 6, isolated line 7L, isolated line 8L, isolated line 7R, isolated line 8R, and continuous line 9.
A 4-way intersection may be considered as occurring at the demarcation Y where it can be seen that a 4-arrowed illustrative figure has been drawn. The 4-way intersection is thus defined as an open region having ends 11, that has a clear line of sight, for example between isolated lines 10L and 11L, between isolated lines 10L and 10R, between isolated lines 10R and 11R, and between isolated lines 11R and 11L. A 3-way intersection maybe considered as occurring in FIG. 1A at the demarcation V where it can be seen that a 3-arrowed illustrative figure has been drawn near end 11. This intersection is thus created by an open region that has a clear line of sight between isolated line 2L and continuous line 1, between continuous line 1 and continuous line 3, and between continuous line 3 and isolated line 2L. Thus, by this definition, an intersection represents the space between a plurality of metallization lines, wherein at least one metallization line has an end that creates at least a portion of the space therebetween.
The metallization lines have been fabricated in the past at a minimum width and as far apart as possible in order to avoid the problems of capacitative coupling and shorting. While the advantages of avoiding capacitative coupling and shorting are preferred, the ever-increasing pressure to miniaturize microelectronic devices influences the design engineer to decrease the overall scale of a metallization line layout. This decrease gives rise to at least three significant problems for the process engineer.
The first significant problem is the focus offset sensitivity or depth of field capability of existing photolithographic exposure equipment. The equipment""s focus offset sensitivity may cause significant problems during patterning of isolated metallization lines. As photolithographic exposure wavelengths become less optimal due to the ever-decreasing scale of the layout, focus offset sensitivity will blur the edges of the metallization line mask. Thereby the entire exposure of the metallization line mask may be excessively blurred, the mask may fail to form, and no metallization line may result. Excessive blurring can cause the problem of an open circuit. This problem may be overcome by widening metallization lines, but widening can be detrimentally offset by the likelihood of short circuiting across metallization lines because nearby closest features may bridge and short or contaminant particles may bridge between metallization lines and create a short circuit.
The second significant problem occurs during fabrication of the metallization lines due to undesired exposure to the masking material and the excess reflectance problems caused by photolithographic light. Light exposure with excess reflectance results in the lateral thinning and/or the recession of a metallization line end of the masking material. Hence, either a thinned, receded, or discontinuous metallization line feature results. Although such excess reflectance may only thin the metallization line feature, thinning thereof will leave the metallization line feature vulnerable to electromigration failure.
In FIG. 1, it can be demonstrated that the excess reflectance problem does not usually occur where any given metallization line such as continuous line 3 has a nearby closest feature 16 such as the proximal edge of isolated line 2L relative to point A upon an edge of continuous line 3. Nearby closest feature 16 an edge of isolated line containing point A is at the distance of xcex10 from point A.
The problem of an excess reflectance may occur for metallization lines where the closest feature is at a distance greater than xcex10. For example, the exposed point C is located upon the same edge of continuous line 3 as point A. Point C is at a lateral-component distance from a nearest neighboring feature that is about evenly spaced between isolated lines 2L and 2R ends 11. Point C has at least one distant closest feature 24 at a distance xcex30, that is greater than distance xcex10. At point C above, and at point Cxe2x80x2 below on continuous line 3, it can be seen that continuous line 3 has respective open exposures, 20 and 21, due to the break in metallization lines that form the intersection between ends 11 of isolated lines 2L and 2R and between isolated lines 4L and 4R. Open exposures 20, 21, can cause excess reflectance at respective points C and Cxe2x80x2.
Excess reflectance can also occur at other structures. In FIG. 1, it can be seen that isolated lines 2L and 4L, when scanned from left to right, each have a first right-angle direction change. For 2L it is downwardly vertical, and for 4L it is upwardly vertical. Each of these direction changes is followed by a second right-angle direction change that restores lines 2L and 4L to run parallel to continuous line 3. Upon continuous line 3 at the point B above, and the point Bxe2x80x2 below, it can be seen that the nearest features thereto are the distant closest features 24 and 25 that each have a diagonal distance of xcex20 between respective points B and Bxe2x80x2 and distant closest features 24 and 25. It can be seen that points B and Bxe2x80x2 upon continuous line 3 also have excess space around them compared to point A. These excess spaces are respective enclosed exposures 18 and 19 of continuous line 3. These exposures are referred to as enclosed exposures because points B and Bxe2x80x2 ultimately have regional metallization line features both above and below, caused in this example by the occurrence of isolated lines 2L and 4L. Enclosed exposures 18 and 19 are likewise detrimental to patterning of the metallization lines similar to open exposures 20 and 21.
Other exposures to occurrences of isolated lines such as isolated lines 5L and 5R include the respective terminal end exposures 22 and 23. Here it can be seen that excess light exposure occurs during photolithographic layout due to the lack of any nearby closest feature 16 such as seen for continuous line 3 at point A.
Because of excess reflectance problems caused by light exposure near such spaces as enclosed exposures 18 and 19, open exposures 20 and 21, and terminal end exposures 22 and 23, there will result an ultimate lateral thinning and/or the recession of an end of the masking material, and either a thinned, receded, or discontinuous metallization line feature for a continuous metallization line. Even though such exposure may not cause a breach in the metallization line feature during fabrication, the thinning of the metallization line will leave the metal line vulnerable to electromigration failure.
The third significant problem caused by miniaturization is an enhanced possibility of an interstitial particulate occurrence or a fabrication error that will cause a bridge to form between adjacent metallization lines, thereby shorting out an associated device and causing the device to fail. The semiconductive device design and process engineer must thus balance the advantage of miniaturization against the disadvantage of causing shorting due to impurity bridging or fabrication imperfection bridging.
What is needed in the art is a metallization design and associated method of fabrication that avoids the problems of the prior art.
The present invention relates to a metallization line layout and fabrication thereof that avoids the creation of metallization line thinning and/or disappearance for excess reflectance-vulnerable metallization line features therein. The present invention accomplishes this objective by taking an existing metallization line layout that has been dictated by the fabrication of a semiconductor device array and by eliminating distant closest features that would otherwise cause the aforementioned problems that existed in the prior art. The method of eliminating distant closest features includes enhancing terminal ends of isolated metallization lines. The method of eliminating distant closest features also includes thickening metallization line widths to achieve substantially only nearby closest features. The method of eliminating distant closest features likewise includes filling spaces between metallization line features to achieve a substantially standard preferred distance between any given metallization line feature and its nearest closest metallization line feature. Additionally, the method of eliminating distant closest features includes staggered unavoidable exposures, after a fashion that causes any given metallization line feature that must have an exposure, to only have a single occurrence thereof on one side of the metallization line. The present invention also includes placing additional xe2x80x9cdummyxe2x80x9d metal shapes in open areas to create a nearby closest feature where the original layout did not provide for such a feature.
The metallization lines may include metals, alloys, and the like. The metallization lines may include doped polysilicon and the like. The metallization lines may include refractory metal nitrides, and the like. The metallization lines may also include superconductive ceramics and the like.
The present invention is carried out by providing a metallization line layout and determining the existence of a space between any point on a metallization line and the nearest feature on the closest neighboring metallization line. Further, a measurement of each such space is taken between the selected point and the nearest feature on the closest neighboring metallization line. Thereafter, it is determined whether the selected point on the metallization line is at a distance from the feature that is greater than a predetermined preferred distance. Where the distance is greater than the predetermined preferred distance, either the metallization line itself, the closest feature, or both are enhanced in size, preferably incrementally and globally, in a direction approaching the preferred distance. Following enhancement, a measurement of the space as enhanced is again taken between the point and its nearest feature. The process is repeated until substantially no nearest feature upon any metallization line is at a distance significantly different from the preferred distance. Additionally, the method assures that any exposure on one side of a metallization line is not coupled with an exposure on the exact opposite side of the metallization line, within a preferred minimal distance. In this way, excess exposure to a metallization line is limited to one side in the area of the exposure.
These and other features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.